Digital components, such as VLSI chips, printed circuit boards and multi-chip modules, are being designed to operate at frequencies exceeding 100 MHz. Typical automatic test equipment (ATE) used for testing digital components in a high-volume production environment currently can perform testing at clock rates only approaching 40 MHz. Testing at lower than the rated frequency or clock rate, however, cannot guarantee proper operation of a digital component at the rated frequency.
A need exists for a method and apparatus for testing complex and high speed digital components at a clock rate that is less than the rated frequency that can guarantee operation at the rated frequency. The rated speed of the most technologically advanced components will, in most circumstances, exceed the capability of the available ATEs, and act as the motivating factor in the development of higher speed ATEs.
ATE designs capable of testing at clock rates around 500 MHz have been shown feasible for further development for a production environment. It is known, however, that the cost of an ATE increases significantly as a function of testing speed, pin count and vector memory required for testing a component. Therefore, the cost of an ATE capable of testing a complex high speed digital component, such as a VLSI, which often has a high pin-count and requires long vector sequences for testing, at the rated frequency would be extremely high. Further, ATE testing performed at frequencies that exceed 20 MHz is influenced by test system noise, which is a source of inaccuracy in the testing.
Built-in self-test (BIST), as described in V. D. Agrawal, C.-J. Lin, P. W. Rutkowski, S. Wu, and Y. Zorian, "Built In Self-Test for Digital Integrated Circuits," AT&T Tech. Jour., Vol. 73, pp. 30-39, March/April 1994, and incorporated by reference herein, is often cited as a solution to the high-speed testing problem. In this method, hardware is added to the digital component for test data generation and response analysis. For instance, a high-speed clock may be supplied from an external ATE while the hardware inside the device under test generates test patterns. Thus, the ATE would not require a large vector memory and a high pin-count capability. The BIST method, however, may not provide an adequate diagnostic or debug capability because the entire test response is compacted into a simple go/no-go signature again by the added response analysis circuitry. In addition, BIST adds substantial and costly hardware to the device. Also, for some high speed components, the extra circuit required for performing BIST cannot be added because it would degrade the high speed of operation of the component.